// 32-bit Shift left by 2
module leftShift2 (in,out);
input [31:0] in;
output [31:0] out;
reg [31:0] out;
out = { in[29:0], 1'b0, 1'b0 };
endmodule // leftShift2
module leftShift2 (in,out);
input [31:0] in;
output [31:0] out;
reg [31:0] out;
out = in << 2;
endmodule
參考來源:
http://inst.eecs.berkeley.edu/~cs61c/fa04/lectures/L26-dg-singlecpu.pdf
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