16-bits Sign Extender to 32-bits

這個Sign Extender主要是希望把16bits的有號數變成32bits的有號數
verilog範例程式如下：

// Sign extender from 16- to 32-bits.
module signExtend (in,out);
input [15:0] in;
output [31:0] out;
reg [31:0] out;
out = { in[15], in[15], in[15], in[15],
in[15], in[15], in[15], in[15],
in[15], in[15], in[15], in[15],
in[15], in[15], in[15], in[15],
in[15:0] };
endmodule // signExtend

另一個比較好的寫法

// Sign Extender
module SignExtend(In, Out);
input [15:0] In;
output [31:0] Out;
assign Out = {{16{In[15]}},In[15:0]};
endmodule

Joint(Concatenation) Operation - Joint different operands as one by { and }
Example 1:
// A = 1'b1, B = 2'b00, C = 2'b10, D = 3'b110
Y = { B, C} // Y is 4'b0010
Y = { A, B, C, D, 3'b001} // Y is 11'b10010110001
Y = { A, B[0], C[1]} // Y is 3'b101
Example 2:
wire [1:0] a, b; wire [2:0] x; wire [3;0] y, Z;
assign x = {1’b0, a}; // x[2]=0, x[1]=a[1], x[0]=a[0]
assign y = {a, b}; /* y[3]=a[1], y[2]=a[0], y[1]=b[1],
y[0]=b[0] */
assign {cout, y} = x + Z; // Concatenation of a result

Replication Operation - Repetition operand several times
Example 1:
A = 1'b1; B = 2'b00; C = 2'b10; D = 3'b110;
Y = { 4{A} } // Y is 4'b1111
Y = { 4{A}, 2{B}, C} //Y is 8'b1111000010

Example 2:
wire [1:0] a, b; wire [4:0] x;
assign x = {2{1’b0}, a}; // Equivalent to x = {0,0,a }
assign y = {2{a}, 3{b}}; //Equivalent to y = {a,a,b,b,b}

有parameter的寫法

<code>module SIGN_EXTEND(in, out);
parameter INSIZE = 16, OUTSIZE = 32;

input [INSIZE-1:0] in;
output [OUTSIZE-1:0] out;
assign out = {{ OUTSIZE-INSIZE {in[INSIZE-1]}}, in};
endmodule // SIGN_EXTEND</code>

資料來源：
berkeley Single Cycle CPU Datapath with Verilog
Multicycle Processor Design in Verilog