Verilog and SystemC 比較

(1)Module的寫法
Verilog
module module_name(input/output declaration)
variable declaration
computation block
endmodule

SystemC
SC_MODULE(module_name){
input/output declaration
internal variable
constructor (computation block)
};

(2)input/output定義
Verilog
Input:input var1, ...;
Output:output var2, ...;
Type

SystemC
Input:sc_in var1, ...;
Output:sc_out var2, ...;
Type

• C++ primitive type: int, float, char, ...
• hardware type: sc_int, sc_uint, ...
• user defined type

(3)Computation Block
Verilog
Event trigger: always@(a or b or c)
Edge trigger: always@(posedge clk)

SystemC
SC_CTOR(module_name){
SC_METHOD(function name);
sensitive << a << b << c;
...
}

參考資料: http://twins.ee.nctu.edu.tw/courses/soc_sys_overview_04fall/lab/systemc_chapter1.ppt